1. Field of the Invention
The present invention relates to plate for forming metal wires and method of forming the metal wires using the same, and more particularly, to a plate for forming metal wires and method of forming the metal wires using the same, in which insulating film patterns of a multi-layer structure are shaped by a single process using a plate in which engraved patterns of wire shapes to be formed are formed and in which the metal wires are formed in trenches and via holes formed in the insulating film patterns by means of the damascene process.
2. Background of the Related Art
A conventional method of forming metal wires in the semiconductor device will be now described by reference to FIG. 1A˜FIG. 1D.
Referring to FIG. 1A, a bottom low-dielectric insulating film 102 is formed on a silicon substrate 101 for which a given process is implemented. An anti-polishing layer 103 is then formed on the bottom low-dielectric insulating film 102. Next, the anti-polishing layer 103 and the bottom low-dielectric insulating film 102 are patterned to form a trench of a given depth. Thereafter, an anti-diffusion film 104 and a copper film are sequentially formed on the entire structure. The copper film and the anti-diffusion film 104 formed on the anti-polishing layer 103 are then removed by means of a chemical mechanical polishing (CMP) process, so copper wires 105 surrounded by the anti-diffusion film 104 are formed within the trench.
By reference to FIG. 1B, top low-dielectric insulating films 106a˜106e of a multi-layer structure are sequentially formed on the entire structure. A mask pattern for forming a via hole 107 is then formed on the top low-dielectric insulating film 106e. Next, the top low-dielectric insulating films 106e˜106b are etched by a given depth by means of an etch process using the mask pattern 107 as an etch mask, thus forming a via hole 108. At this time, the top low-dielectric insulating film 106a is used as an etch stop layer.
With reference to FIG. 1C, after the mask pattern 107 is removed, a mask pattern 109 for forming the trench is formed on the top low-dielectric insulating film 106e. The top low-dielectric insulating films 106e and 106d are then etched by means of an etch process using the mask pattern 109 as an etch mask, thereby forming a trench 110. At the same time, remaining top low-dielectric insulating film 106a is etched to complete the via hole 108 so that the copper wires 105 are exposed. At this time, the top low-dielectric insulating film 106c is used as the etch stop layer.
Referring to FIG. 1D, an anti-diffusion film 11 and a copper film (not shown) are sequentially formed on the entire structure including the trench 110 and the via hole 108. The copper film and the anti-diffusion film 11 deposited on the top low-dielectric insulating film 6e are then removed by means of a chemical mechanical polishing (CMP) process, so that copper wires 12 surrounded by the anti-diffusion film 11 is formed within the trench. The copper wires 12 are connected to the copper wires 105 via the via hole 108.
In the conventional method of forming the metal wires of a multi-layer structure using the damascene process, however, there occur several problems due to diffused reflection, flatness of the surface, etc., which are caused by the underlying copper wires during the photolithography process for forming the via hole or the trench. For this reason, there is lots of difficulty in forming a pattern of an ultra-fine size. Furthermore, during the etch process, as the low-dielectric insulating film is lost or the pattern is crumpled, fail is caused. Due to this, in order to form wires of a multi-layer structure, multi-step photolithography and etch processes must be implemented.